A liquid crystal display (LCD) is a flat-panel display that has a number of advantageous features including high resolution, drastically reduced thickness and weight, and low power dissipation. The LCD market has been rapidly expanding recently as a result of tremendous improvements in its display performance, significant increases in its productivity, and a noticeable rise in its cost effectiveness over competing technologies.
Among other things, in-plane switching (IPS) mode LCDs (see Patent Document No. 1, for example) and multi-domain vertical aligned (MVA) mode LCDs (see Patent Document No. 2, for example) have been used as liquid crystal display devices with a wide viewing angle characteristic, of which the contrast ratio on the screen does not decrease significantly, or of which the display grayscale does not invert, even when the image on the screen is viewed obliquely, in liquid crystal TV sets.
Although the display qualities of LCDs have been further improved nowadays, the problem of varying the γ characteristic with the viewing angle has arisen just recently. That is to say, the γ characteristic when an image on the screen is viewed straight is different from the characteristic when it is viewed obliquely. As used herein, the “γ characteristic” refers to the grayscale dependence of display luminance. That is why if the γ characteristic when the image is viewed straight is different from the characteristic when the same image is viewed obliquely, then it means that the grayscale display state changes according to the viewing direction. This is a serious problem particularly when a still picture such as a photo is presented or when a TV program is displayed.
The viewing angle dependence of the γ characteristic is more significant in the MVA mode rather than in the IPS mode. According to the IPS mode, however, it is more difficult to make panels that realize a high contrast ratio when the image on the screen is viewed straight with good productivity rather than in the MVA mode. Taking these circumstances into consideration, it is particularly necessary to reduce the viewing angle dependence of the γ characteristic of MVA mode liquid crystal display devices, among other things.
To overcome such a problem, the applicant (or the assignee) of the present application disclosed a liquid crystal display device that can reduce the viewing angle dependence of the γ characteristic (or an whitening phenomenon of an image among other things) by dividing a single pixel into a number of subpixels with mutually different brightness values, and a method for driving such a device in Patent Document No. 3. Such a display or drive mode will sometimes be referred to herein as “area-grayscale display”, “area-grayscale drive”, “multi-pixel display” or “multi-pixel drive”.
Patent Document No. 3 discloses a liquid crystal display device in which storage capacitors CS are provided for respective subpixels SP of a single pixel P. In the storage capacitors, the storage capacitor counter electrodes (which are connected to storage capacitor lines) are electrically independent of each other between the subpixels. And by varying the voltages applied to the storage capacitor counter electrodes (which will be referred to herein as “storage capacitor counter voltages” or “CS signal voltages”), mutually different effective voltages can be applied to the respective liquid crystal layers of multiple subpixels by utilizing a capacitance division technique.
Hereinafter, the pixel division structure of the liquid crystal display device 900 disclosed in Patent Document No. 3 will be described with reference to FIG. 47. In this example, a liquid crystal display device including TFTs as switching elements will be described.
The pixel 10 is split into a subpixel 10a and another subpixel 10b. To the subpixels 10a and 10b, connected are their associated TFTs 16a and 16b and their associated storage capacitors (CS) 22a and 22b, respectively. The gate electrodes of the TFTs 16a and 16b are both connected to the same scan line 12 (which will also be referred to herein as a “gate bus line” or “G bus line”). And the source electrodes of the TFTs 16a and 16b are connected to the same signal line (which will also be referred to herein as a “source bus line” or “S bus line”). The storage capacitors 22a and 22b are connected to their associated storage capacitor lines (CS bus lines) 24a and 24b, respectively. The storage capacitor 22a includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18a, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24a, and an insulating layer (not shown) arranged between the electrodes. The storage capacitor 22b includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18b, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24b, and an insulating layer (not shown) arranged between the electrodes. The respective storage capacitor counter electrodes of the storage capacitors 22a and 22b are independent of each other and have such a structure as receiving mutually different storage capacitor counter voltages (CS signal voltages) from the storage capacitor lines 24a and 24b, respectively.
Hereinafter, the principle on which mutually different effective voltages can be applied to the respective liquid crystal layers of the two subpixels 10a and 10b of the liquid crystal display device 900 will be described with reference to the accompanying drawings.
FIG. 48 schematically shows the equivalent circuit of one pixel of the liquid crystal display device 900. In this electrical equivalent circuit, the liquid crystal capacitors of the respective subpixels SP-A. (10a) and SP-B (10b) are identified by CLC-A (13a) and CLC-B (13b), respectively. Each of these liquid crystal capacitors CLC-A and CLC-B includes a subpixel electrode 18a, 18b, a liquid crystal layer, and a counter electrode (that is shared by the subpixel electrodes 18a and 18b).
The liquid crystal capacitors CLC-A and CLC-B are supposed to have the same electrostatic capacitance CLC (V). The value of CLC (V) depends on the effective voltages (V) applied to the liquid crystal layers of the respective subpixels SP-A and SP-B. Also, the storage capacitors CCS-A (22a) and CCS-B (22b) that are connected independently of each other to the liquid crystal capacitors of the respective subpixels SP-A and SP-B are supposed to have the same electrostatic capacitance CCS.
In the subpixel SP-A, one electrode of the liquid crystal capacitor CLC-A and one electrode of the storage capacitor CCS-A are connected to the drain electrode of the TFT-A (16a), which is provided to drive the subpixel SP-A. The other electrode of the liquid crystal capacitor CLC-A is connected to the counter electrode. And the other electrode of the storage capacitor CCS-A is connected to the storage capacitor line CS-A (24a). In the subpixel SP-B, one electrode of the liquid crystal capacitor CLC-B and one electrode of the storage capacitor CCS-B are connected to the drain electrode of the TFT-B (16b), which is provided to drive the subpixel SP-B. The other electrode of the liquid crystal capacitor CLC-B is connected to the counter electrode. And the other electrode of the storage capacitor CCS-B is connected to the storage capacitor line CS-B (24b). The gate electrodes of the TFT-A and TFT-B are both connected to the G bus line (scan line) 12 and the source electrodes thereof are both connected to the S bus line (signal line) 14.
Portions (a) through (f) of FIG. 49 schematically show the timings to apply respective voltages to drive the liquid crystal display device 900.
Specifically, portion (a) of FIG. 49 shows the voltage waveform Vs of the S bus line 14; portion (b) of FIG. 49 shows the voltage waveform Vcsa of the CS bus line CS-A; portion (c) of FIG. 49 shows the voltage waveform Vcsb of the CS bus line CS-B; portion (d) of FIG. 49 shows the voltage waveform Vg of the G bus line 12; portion (e) of FIG. 49 shows the voltage waveform Vlca of the subpixel electrode 18a; and portion (f) of FIG. 49 shows the voltage waveform Vlcb of the subpixel electrode 18b. In FIG. 49, the dashed line indicates the voltage waveform COMMON (Vcom) of the counter electrode.
Hereinafter, it will be described with reference to portions (a) through (f) of FIG. 49 how the equivalent circuit shown in FIG. 48 operates.
First, at a time T1, the voltage Vg rises from VgL to VgH to turn the TFT-A and TFT-B ON simultaneously. As a result, the voltage Vs on the S bus line 14 is transmitted to the subpixel electrodes 18a and 18b to charge the liquid crystal capacitors CLC-A and CLC-B of the subpixels SP-A and SP-B with the voltage Vs. In the same way, the storage capacitors CCS-A and CCS-B of the respective subpixels are also charged with the voltage on the S bus line 14.
Next, at a time T2, the voltage Vg on the G bus line 12 falls from VgH to VgL to turn the TFT-A and TFT-B OFF simultaneously and electrically isolate the liquid crystal capacitors CLC-A and CLC-B of the subpixels SP-A and SP-B and the storage capacitors CCS-A and CCS-B from the S bus line 14. It should be noted that immediately after that, due to the feedthrough phenomenon caused by parasitic capacitances of the TFT-A and TFT-B and other factors, the voltages Vlca and Vlcb applied to the respective subpixel electrodes decrease by approximately the same voltage Vd to:Vlca=Vs−Vd Vlcb=Vs−Vd respectively. Also, in this case, the voltages Vcsa and Vcsb on the CS bus lines are:Vcsa=Vcom−Vad Vcsb=Vcom+Vad respectively.
Next, at a time T3, the voltage Vcsa on the CS bus line CS-A connected to the storage capacitor CCS-A rises from Vcom−Vad to Vcom+Vad and the voltage Vcsb on the CS bus line CS-8 connected to the storage capacitor Csb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad. As the voltages on the CS bus lines CS-A and CS-B change in this manner, the voltages Vlca and Vlcb applied to the respective subpixel electrodes change into:Vlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad respectively, where Kc=CCS/(CLC(V)+CCS) and × is the symbol of multiplication.
Next, at a time T4, Vcsa falls from Vcom+Vad to Vcom−Vad and Vcsb rises from Vcom−Vad to Vcom+Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change fromVlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad intoVlca=Vs−Vd Vlcb=Vs−Vd respectively.
Next, at a time T5, Vcsa rises from Vcom−Vad to Vcom+Vad and Vcsb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change fromVlca=Vs−Vd Vlcb=Vs−Vd intoVlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad respectively.
After that, every time a period of time that is an integral number of times as long as one horizontal scanning period (or one horizontal write period) 1H has passed, the voltages Vcsa, Vcsb, Vlca and Vlcb alternate their levels at the times T4 and T5. Consequently, the effective values of the voltages Vlca and Vlcb applied to the subpixel electrodes become:Vlca=Vs−Vd+Kc×Vad Vlcb=Vs−Vd−Kc×Vad respectively.
Therefore, the effective voltages V1 and V2 applied to the liquid crystal layers 13a and 13b of the subpixels SP-A and SP-B become:V1=Vlca−Vcom V2=Vlcb−Vcom That is to say,V1=Vs−Vd+Kc×Vad−Vcom V2=Vs−Vd−Kc×Vad−Vcom respectively.
As a result, the difference ΔV12 (=V1−V2) between the effective voltages applied to the liquid crystal layers 13a and 13b of the subpixels SP-A and SP-B becomes ΔV12==2×Kc×Vad (where Kc=CCS/(CLC(V)+CCS)). Thus, mutually different voltages can be applied to the liquid crystal layers 13a and 13b. 
FIG. 50 schematically shows the relation between V1 and V2. As can be seen from FIG. 50, the smaller the V1 value, the bigger ΔV12 in the liquid crystal display device 900. Since ΔV12 increases as the V1 value decreases in this manner, the whitening phenomenon can be reduced, among other things.
However, if the multi-pixel structure disclosed in Patent Document No. 3 is applied to either a high-definition LCD TV monitor or a large-screen LCD TV monitor, the following problem will arise. Specifically, as the definition or the screen size of a display panel increases, the oscillating voltage comes to have an even shorter period of oscillation. Consequently, it becomes increasingly difficult (and expensive) to make a circuit for generating the oscillating voltage, the power dissipation will increase too much, or the influence of waveform blunting due to the electrical load impedance of the CS bus lines will be more and more significant. Nevertheless, if a plurality of electrically independent CS trunks are arranged and connected to the multiple CS bus lines as disclosed in Patent Document No. 4, one period of oscillation of the oscillating voltage applied to the storage capacitor counter electrodes via the CS bus lines can be extended. The entire disclosures of Patent Documents Nos. 3 and 4 are hereby incorporated by reference.    Patent Document No. 1: Japanese Patent Gazette for Opposition No. 63-21907    Patent Document No. 2: Japanese Patent Application Laid-Open Publication No. 11-242225    Patent Document No. 3: Japanese Patent Application Laid-Open Publication No. 2004-62146 (corresponding to U.S. Pat. No. 6,958,791)    Patent Document No. 4: WO 2006/070829 A1